Does the icache (of the rocket core) read the instructions through the crossbar network in rocketchip?












0















I am working on removing the crossbar network in rocketchip. But I don't know what the side effects will be. I have a 2D mesh connecting the cores to each other (I integrated it with an interface between the core and the memory (dCacheArbiter)). I want all the cores to access all the uncore components, which are on the crossbar network, through core0. Therefore I would like to remove all the crossbar connections except the ones between core0 and the uncore components.



So does the iCache fetch the instructions from the memory through the crossbar network? Because I cannot see any direct connection between the iCache and scratchpad memory (I use scratchpad instead of dCache). Actually I am not sure about where the instructions are stored. In the linker I placed the .text of each core on the address of local scratchpads. (I do baremetal.)



Thanks,






riscv rocket-chip







share|improve this question



























    0















    I am working on removing the crossbar network in rocketchip. But I don't know what the side effects will be. I have a 2D mesh connecting the cores to each other (I integrated it with an interface between the core and the memory (dCacheArbiter)). I want all the cores to access all the uncore components, which are on the crossbar network, through core0. Therefore I would like to remove all the crossbar connections except the ones between core0 and the uncore components.



    So does the iCache fetch the instructions from the memory through the crossbar network? Because I cannot see any direct connection between the iCache and scratchpad memory (I use scratchpad instead of dCache). Actually I am not sure about where the instructions are stored. In the linker I placed the .text of each core on the address of local scratchpads. (I do baremetal.)



    Thanks,






    riscv rocket-chip







    share|improve this question

























      0












      0








      0








      I am working on removing the crossbar network in rocketchip. But I don't know what the side effects will be. I have a 2D mesh connecting the cores to each other (I integrated it with an interface between the core and the memory (dCacheArbiter)). I want all the cores to access all the uncore components, which are on the crossbar network, through core0. Therefore I would like to remove all the crossbar connections except the ones between core0 and the uncore components.



      So does the iCache fetch the instructions from the memory through the crossbar network? Because I cannot see any direct connection between the iCache and scratchpad memory (I use scratchpad instead of dCache). Actually I am not sure about where the instructions are stored. In the linker I placed the .text of each core on the address of local scratchpads. (I do baremetal.)



      Thanks,






      riscv rocket-chip







      share|improve this question














      I am working on removing the crossbar network in rocketchip. But I don't know what the side effects will be. I have a 2D mesh connecting the cores to each other (I integrated it with an interface between the core and the memory (dCacheArbiter)). I want all the cores to access all the uncore components, which are on the crossbar network, through core0. Therefore I would like to remove all the crossbar connections except the ones between core0 and the uncore components.



      So does the iCache fetch the instructions from the memory through the crossbar network? Because I cannot see any direct connection between the iCache and scratchpad memory (I use scratchpad instead of dCache). Actually I am not sure about where the instructions are stored. In the linker I placed the .text of each core on the address of local scratchpads. (I do baremetal.)



      Thanks,






      riscv rocket-chip




      riscv rocket-chip






      share|improve this question













      share|improve this question











      share|improve this question




      share|improve this question










      asked Nov 16 '18 at 12:31









      Suleyman SavasSuleyman Savas

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