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Am I calculating total input capacitance or gate capacitance or none of the above? And are my calculations even correct to begin with. The point of this is that I want to know what gate capacitance im dealing with to properly chose a gate resistor to give me the rise time I need, more or less.

So I have the following circuit using the old IRF540

^{simulate this circuit – Schematic created using CircuitLab}

I am probing the gate directly and get the following readings:

I am loosing 500 mV somewhere but anyways:

My voltage at 1 time constant is:
(This is where the dashed vertical line is)

So measuring the time from 0 V (solid vertical line) to the 1 time constant line (dashed) you can see is about 530 ns. So my time constant is 530 ns and the gate resistor is 100 ohm then:

Is my logic correct that this is my input capacitance? And given will this vary if I have same Vds but a Vgs that is NOT equal to Vds?

Extra points: Where are my 500 mV?

You are measuring the lump capacitance in accord with this standard model,

You even have observed the Miller Plateau.

The capacitances do depend on applied voltages however, see this ROHM article. As VDS increases the capacitance decreases.

Brief description of methods used to characterize individual capacitances can be found in this Vishay Siliconix appnote AN-957, see Fig.17, 18, and 19. Three configurations of a capacitance bridge are used, and then individual caps are algebraically determined.