My linux c++ gnu makefile variable expansion does not behave as I expected it to
I have created the following little makefile snippet. Note: I have made this a minimal example of my problem so it is a pointless makefile.
TARGET = none
OBJ_BASE_DIR = obj
# Linux x86 c++ compiler
.PHONY: build_cpp_x86Linux
build_cpp_x86Linux: TARGET = x86Linux
build_cpp_x86Linux: build
OBJ_DIR = $(addsuffix /$(TARGET),$(OBJ_BASE_DIR))
$(info TARGET IS: $(TARGET))
$(info OBJ_DIR IS: $(OBJ_DIR))
build: $(OBJ_DIR)/test.o
@echo building, OBJ_DIR: $(OBJ_DIR)
# pattern rule
$(OBJ_DIR)/%.o:
@echo "compiling $@"
Here is the output of calling make
:
TARGET IS: none
OBJ_DIR IS: obj/none
compiling obj/none/test.o
building, OBJ_DIR: obj/x86Linux
From the output you can see that it is trying to compile obj/none/test.o
, but what I want it to do is try to compile obj/x86Linux/test.o
. I am not quite sure what is going on here. I think I understand that the makefile expands the variables on the first pass (which would result in TARGET=none), but I thought that it would re-expand the variables again once I have called the target build_cpp_x86Linux
which sets the value of TARGET to x86Linux...
What I am doing wrong here and how should this be done?
c++ linux makefile
|
show 6 more comments
I have created the following little makefile snippet. Note: I have made this a minimal example of my problem so it is a pointless makefile.
TARGET = none
OBJ_BASE_DIR = obj
# Linux x86 c++ compiler
.PHONY: build_cpp_x86Linux
build_cpp_x86Linux: TARGET = x86Linux
build_cpp_x86Linux: build
OBJ_DIR = $(addsuffix /$(TARGET),$(OBJ_BASE_DIR))
$(info TARGET IS: $(TARGET))
$(info OBJ_DIR IS: $(OBJ_DIR))
build: $(OBJ_DIR)/test.o
@echo building, OBJ_DIR: $(OBJ_DIR)
# pattern rule
$(OBJ_DIR)/%.o:
@echo "compiling $@"
Here is the output of calling make
:
TARGET IS: none
OBJ_DIR IS: obj/none
compiling obj/none/test.o
building, OBJ_DIR: obj/x86Linux
From the output you can see that it is trying to compile obj/none/test.o
, but what I want it to do is try to compile obj/x86Linux/test.o
. I am not quite sure what is going on here. I think I understand that the makefile expands the variables on the first pass (which would result in TARGET=none), but I thought that it would re-expand the variables again once I have called the target build_cpp_x86Linux
which sets the value of TARGET to x86Linux...
What I am doing wrong here and how should this be done?
c++ linux makefile
1
Note:.PHONEY
-->.PHONY
.
– G.M.
Nov 18 '18 at 20:03
@G.M. good spot.. fixed
– code_fodder
Nov 18 '18 at 20:11
1
It's possible to fix this with second-expansion, but you really shouldn't use targets for the job of a makefile. And if you do want to use targets, call another makefile recursively.
– o11c
Nov 18 '18 at 20:43
@o11c hmm.... how can this be solved with second-expansion?, I took a look at this but could not quite figure out how to use it for this purpose. Also re: calling makefile I don't get if you mean call the "makefile recursively" or "call another makefile".... I think I get how each of those could work (by passing variables into the second makefile call... : )
– code_fodder
Nov 18 '18 at 20:48
Is "none" even a real value, or is it just a dummy?
– amn
Nov 18 '18 at 21:00
|
show 6 more comments
I have created the following little makefile snippet. Note: I have made this a minimal example of my problem so it is a pointless makefile.
TARGET = none
OBJ_BASE_DIR = obj
# Linux x86 c++ compiler
.PHONY: build_cpp_x86Linux
build_cpp_x86Linux: TARGET = x86Linux
build_cpp_x86Linux: build
OBJ_DIR = $(addsuffix /$(TARGET),$(OBJ_BASE_DIR))
$(info TARGET IS: $(TARGET))
$(info OBJ_DIR IS: $(OBJ_DIR))
build: $(OBJ_DIR)/test.o
@echo building, OBJ_DIR: $(OBJ_DIR)
# pattern rule
$(OBJ_DIR)/%.o:
@echo "compiling $@"
Here is the output of calling make
:
TARGET IS: none
OBJ_DIR IS: obj/none
compiling obj/none/test.o
building, OBJ_DIR: obj/x86Linux
From the output you can see that it is trying to compile obj/none/test.o
, but what I want it to do is try to compile obj/x86Linux/test.o
. I am not quite sure what is going on here. I think I understand that the makefile expands the variables on the first pass (which would result in TARGET=none), but I thought that it would re-expand the variables again once I have called the target build_cpp_x86Linux
which sets the value of TARGET to x86Linux...
What I am doing wrong here and how should this be done?
c++ linux makefile
I have created the following little makefile snippet. Note: I have made this a minimal example of my problem so it is a pointless makefile.
TARGET = none
OBJ_BASE_DIR = obj
# Linux x86 c++ compiler
.PHONY: build_cpp_x86Linux
build_cpp_x86Linux: TARGET = x86Linux
build_cpp_x86Linux: build
OBJ_DIR = $(addsuffix /$(TARGET),$(OBJ_BASE_DIR))
$(info TARGET IS: $(TARGET))
$(info OBJ_DIR IS: $(OBJ_DIR))
build: $(OBJ_DIR)/test.o
@echo building, OBJ_DIR: $(OBJ_DIR)
# pattern rule
$(OBJ_DIR)/%.o:
@echo "compiling $@"
Here is the output of calling make
:
TARGET IS: none
OBJ_DIR IS: obj/none
compiling obj/none/test.o
building, OBJ_DIR: obj/x86Linux
From the output you can see that it is trying to compile obj/none/test.o
, but what I want it to do is try to compile obj/x86Linux/test.o
. I am not quite sure what is going on here. I think I understand that the makefile expands the variables on the first pass (which would result in TARGET=none), but I thought that it would re-expand the variables again once I have called the target build_cpp_x86Linux
which sets the value of TARGET to x86Linux...
What I am doing wrong here and how should this be done?
c++ linux makefile
c++ linux makefile
edited Nov 18 '18 at 20:11
code_fodder
asked Nov 18 '18 at 19:51
code_foddercode_fodder
5,22463775
5,22463775
1
Note:.PHONEY
-->.PHONY
.
– G.M.
Nov 18 '18 at 20:03
@G.M. good spot.. fixed
– code_fodder
Nov 18 '18 at 20:11
1
It's possible to fix this with second-expansion, but you really shouldn't use targets for the job of a makefile. And if you do want to use targets, call another makefile recursively.
– o11c
Nov 18 '18 at 20:43
@o11c hmm.... how can this be solved with second-expansion?, I took a look at this but could not quite figure out how to use it for this purpose. Also re: calling makefile I don't get if you mean call the "makefile recursively" or "call another makefile".... I think I get how each of those could work (by passing variables into the second makefile call... : )
– code_fodder
Nov 18 '18 at 20:48
Is "none" even a real value, or is it just a dummy?
– amn
Nov 18 '18 at 21:00
|
show 6 more comments
1
Note:.PHONEY
-->.PHONY
.
– G.M.
Nov 18 '18 at 20:03
@G.M. good spot.. fixed
– code_fodder
Nov 18 '18 at 20:11
1
It's possible to fix this with second-expansion, but you really shouldn't use targets for the job of a makefile. And if you do want to use targets, call another makefile recursively.
– o11c
Nov 18 '18 at 20:43
@o11c hmm.... how can this be solved with second-expansion?, I took a look at this but could not quite figure out how to use it for this purpose. Also re: calling makefile I don't get if you mean call the "makefile recursively" or "call another makefile".... I think I get how each of those could work (by passing variables into the second makefile call... : )
– code_fodder
Nov 18 '18 at 20:48
Is "none" even a real value, or is it just a dummy?
– amn
Nov 18 '18 at 21:00
1
1
Note:
.PHONEY
--> .PHONY
.– G.M.
Nov 18 '18 at 20:03
Note:
.PHONEY
--> .PHONY
.– G.M.
Nov 18 '18 at 20:03
@G.M. good spot.. fixed
– code_fodder
Nov 18 '18 at 20:11
@G.M. good spot.. fixed
– code_fodder
Nov 18 '18 at 20:11
1
1
It's possible to fix this with second-expansion, but you really shouldn't use targets for the job of a makefile. And if you do want to use targets, call another makefile recursively.
– o11c
Nov 18 '18 at 20:43
It's possible to fix this with second-expansion, but you really shouldn't use targets for the job of a makefile. And if you do want to use targets, call another makefile recursively.
– o11c
Nov 18 '18 at 20:43
@o11c hmm.... how can this be solved with second-expansion?, I took a look at this but could not quite figure out how to use it for this purpose. Also re: calling makefile I don't get if you mean call the "makefile recursively" or "call another makefile".... I think I get how each of those could work (by passing variables into the second makefile call... : )
– code_fodder
Nov 18 '18 at 20:48
@o11c hmm.... how can this be solved with second-expansion?, I took a look at this but could not quite figure out how to use it for this purpose. Also re: calling makefile I don't get if you mean call the "makefile recursively" or "call another makefile".... I think I get how each of those could work (by passing variables into the second makefile call... : )
– code_fodder
Nov 18 '18 at 20:48
Is "none" even a real value, or is it just a dummy?
– amn
Nov 18 '18 at 21:00
Is "none" even a real value, or is it just a dummy?
– amn
Nov 18 '18 at 21:00
|
show 6 more comments
1 Answer
1
active
oldest
votes
You could also use:
TARGET?=none
And then override on the command line TARGET=x86Linux
You can also use ifdef
or other scanning if
operations to set different variables based on these arguments or environment variables.
Similar comment to MadScientists comment. Upvoted since it does work, but not quite right yet for me. But I think from what I have read so far a good approach for me is to have another layer of makefile to set these target variables and then call make again on another makefile or some such....
– code_fodder
Nov 18 '18 at 22:59
add a comment |
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1 Answer
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1 Answer
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active
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oldest
votes
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oldest
votes
You could also use:
TARGET?=none
And then override on the command line TARGET=x86Linux
You can also use ifdef
or other scanning if
operations to set different variables based on these arguments or environment variables.
Similar comment to MadScientists comment. Upvoted since it does work, but not quite right yet for me. But I think from what I have read so far a good approach for me is to have another layer of makefile to set these target variables and then call make again on another makefile or some such....
– code_fodder
Nov 18 '18 at 22:59
add a comment |
You could also use:
TARGET?=none
And then override on the command line TARGET=x86Linux
You can also use ifdef
or other scanning if
operations to set different variables based on these arguments or environment variables.
Similar comment to MadScientists comment. Upvoted since it does work, but not quite right yet for me. But I think from what I have read so far a good approach for me is to have another layer of makefile to set these target variables and then call make again on another makefile or some such....
– code_fodder
Nov 18 '18 at 22:59
add a comment |
You could also use:
TARGET?=none
And then override on the command line TARGET=x86Linux
You can also use ifdef
or other scanning if
operations to set different variables based on these arguments or environment variables.
You could also use:
TARGET?=none
And then override on the command line TARGET=x86Linux
You can also use ifdef
or other scanning if
operations to set different variables based on these arguments or environment variables.
answered Nov 18 '18 at 20:35
Matthieu BrucherMatthieu Brucher
15.6k32140
15.6k32140
Similar comment to MadScientists comment. Upvoted since it does work, but not quite right yet for me. But I think from what I have read so far a good approach for me is to have another layer of makefile to set these target variables and then call make again on another makefile or some such....
– code_fodder
Nov 18 '18 at 22:59
add a comment |
Similar comment to MadScientists comment. Upvoted since it does work, but not quite right yet for me. But I think from what I have read so far a good approach for me is to have another layer of makefile to set these target variables and then call make again on another makefile or some such....
– code_fodder
Nov 18 '18 at 22:59
Similar comment to MadScientists comment. Upvoted since it does work, but not quite right yet for me. But I think from what I have read so far a good approach for me is to have another layer of makefile to set these target variables and then call make again on another makefile or some such....
– code_fodder
Nov 18 '18 at 22:59
Similar comment to MadScientists comment. Upvoted since it does work, but not quite right yet for me. But I think from what I have read so far a good approach for me is to have another layer of makefile to set these target variables and then call make again on another makefile or some such....
– code_fodder
Nov 18 '18 at 22:59
add a comment |
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1
Note:
.PHONEY
-->.PHONY
.– G.M.
Nov 18 '18 at 20:03
@G.M. good spot.. fixed
– code_fodder
Nov 18 '18 at 20:11
1
It's possible to fix this with second-expansion, but you really shouldn't use targets for the job of a makefile. And if you do want to use targets, call another makefile recursively.
– o11c
Nov 18 '18 at 20:43
@o11c hmm.... how can this be solved with second-expansion?, I took a look at this but could not quite figure out how to use it for this purpose. Also re: calling makefile I don't get if you mean call the "makefile recursively" or "call another makefile".... I think I get how each of those could work (by passing variables into the second makefile call... : )
– code_fodder
Nov 18 '18 at 20:48
Is "none" even a real value, or is it just a dummy?
– amn
Nov 18 '18 at 21:00