Passing an 8-bit value to a 1-bit port?












0















I'm using System Verilog. My top-level design file has a 1-bit output bsOut. I'm also using a register called shift_reg, which outputs an 8-bit number from the port dOut. I want to do this:



module FinalTop (
input clk,
output bsOut
);
Shift_Reg shift_reg(.clk(clk), .dOut(bsOut));


I believe that Vivado/Basys3 will truncate dOut by using only the LSB --> bsOut, but what if I want to specify a different bit? For example, what if I want to send .dOut[7](bsOut)? Obviously this won't work (I tried), but I don't know how to do it properly. I could make a logic [7:0] dOutTemp = dOut, then assign bsOut = dOutTemp[7];, but this seems clunky.










share|improve this question

























  • You need to shift bits. In C, that would be d0ut >> 7

    – iPirat
    Nov 17 '18 at 5:32
















0















I'm using System Verilog. My top-level design file has a 1-bit output bsOut. I'm also using a register called shift_reg, which outputs an 8-bit number from the port dOut. I want to do this:



module FinalTop (
input clk,
output bsOut
);
Shift_Reg shift_reg(.clk(clk), .dOut(bsOut));


I believe that Vivado/Basys3 will truncate dOut by using only the LSB --> bsOut, but what if I want to specify a different bit? For example, what if I want to send .dOut[7](bsOut)? Obviously this won't work (I tried), but I don't know how to do it properly. I could make a logic [7:0] dOutTemp = dOut, then assign bsOut = dOutTemp[7];, but this seems clunky.










share|improve this question

























  • You need to shift bits. In C, that would be d0ut >> 7

    – iPirat
    Nov 17 '18 at 5:32














0












0








0








I'm using System Verilog. My top-level design file has a 1-bit output bsOut. I'm also using a register called shift_reg, which outputs an 8-bit number from the port dOut. I want to do this:



module FinalTop (
input clk,
output bsOut
);
Shift_Reg shift_reg(.clk(clk), .dOut(bsOut));


I believe that Vivado/Basys3 will truncate dOut by using only the LSB --> bsOut, but what if I want to specify a different bit? For example, what if I want to send .dOut[7](bsOut)? Obviously this won't work (I tried), but I don't know how to do it properly. I could make a logic [7:0] dOutTemp = dOut, then assign bsOut = dOutTemp[7];, but this seems clunky.










share|improve this question
















I'm using System Verilog. My top-level design file has a 1-bit output bsOut. I'm also using a register called shift_reg, which outputs an 8-bit number from the port dOut. I want to do this:



module FinalTop (
input clk,
output bsOut
);
Shift_Reg shift_reg(.clk(clk), .dOut(bsOut));


I believe that Vivado/Basys3 will truncate dOut by using only the LSB --> bsOut, but what if I want to specify a different bit? For example, what if I want to send .dOut[7](bsOut)? Obviously this won't work (I tried), but I don't know how to do it properly. I could make a logic [7:0] dOutTemp = dOut, then assign bsOut = dOutTemp[7];, but this seems clunky.







system-verilog vivado






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edited Nov 17 '18 at 6:02









dave_59

19.9k21537




19.9k21537










asked Nov 17 '18 at 5:27









Alex GAlex G

3903918




3903918













  • You need to shift bits. In C, that would be d0ut >> 7

    – iPirat
    Nov 17 '18 at 5:32



















  • You need to shift bits. In C, that would be d0ut >> 7

    – iPirat
    Nov 17 '18 at 5:32

















You need to shift bits. In C, that would be d0ut >> 7

– iPirat
Nov 17 '18 at 5:32





You need to shift bits. In C, that would be d0ut >> 7

– iPirat
Nov 17 '18 at 5:32












1 Answer
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You can use a port expression.



module FinalTop (
input clk,
output .bsOut(dOut[7])
);
logic [7:0] dOut;
Shift_Reg shift_reg(.clk, .dOut);


Note that .clk is equivalent to .clk(clk), etc.






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    1 Answer
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    1














    You can use a port expression.



    module FinalTop (
    input clk,
    output .bsOut(dOut[7])
    );
    logic [7:0] dOut;
    Shift_Reg shift_reg(.clk, .dOut);


    Note that .clk is equivalent to .clk(clk), etc.






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      1














      You can use a port expression.



      module FinalTop (
      input clk,
      output .bsOut(dOut[7])
      );
      logic [7:0] dOut;
      Shift_Reg shift_reg(.clk, .dOut);


      Note that .clk is equivalent to .clk(clk), etc.






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        1







        You can use a port expression.



        module FinalTop (
        input clk,
        output .bsOut(dOut[7])
        );
        logic [7:0] dOut;
        Shift_Reg shift_reg(.clk, .dOut);


        Note that .clk is equivalent to .clk(clk), etc.






        share|improve this answer













        You can use a port expression.



        module FinalTop (
        input clk,
        output .bsOut(dOut[7])
        );
        logic [7:0] dOut;
        Shift_Reg shift_reg(.clk, .dOut);


        Note that .clk is equivalent to .clk(clk), etc.







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        answered Nov 17 '18 at 6:07









        dave_59dave_59

        19.9k21537




        19.9k21537






























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