Make: How pre-requs are creating automatically?
I am new to make. I am trying to debug some issue. For that i kept some debug statements to know all pre-reqs of particular target.
Eg:
$(TARGET_BUILD)/%.o: $(TARGET_BUILD)/%.c
$(info pre-res for this target $^)
$(c_dependency)
After completion of the build. When i check the build log i can see there are several '.h' files listed in prerequisites. From the above target we mentioned only '.c' ($(TARGET_BUILD)/%.c) files as pre-reqs right? Then how come it is showing header files in pre-reqs. Are they auto generated? If yes, Can you please help me how they are created automatically.
FYI, $(c_dependency) is a define directive which has below lines defined :
mkdir -p $(@D)
$(CC64) -o $(@) -c $(CFLAGS64) $<
makefile gnu-make
asked Nov 23 '18 at 6:47
santoshsantosh
495
add a comment |
I am new to make. I am trying to debug some issue. For that i kept some debug statements to know all pre-reqs of particular target.
Eg:
$(TARGET_BUILD)/%.o: $(TARGET_BUILD)/%.c
$(info pre-res for this target $^)
$(c_dependency)
After completion of the build. When i check the build log i can see there are several '.h' files listed in prerequisites. From the above target we mentioned only '.c' ($(TARGET_BUILD)/%.c) files as pre-reqs right? Then how come it is showing header files in pre-reqs. Are they auto generated? If yes, Can you please help me how they are created automatically.
FYI, $(c_dependency) is a define directive which has below lines defined :
mkdir -p $(@D)
$(CC64) -o $(@) -c $(CFLAGS64) $<
makefile gnu-make
asked Nov 23 '18 at 6:47
santoshsantosh
495
You probably have other rules without recipe, elsewhere in this Makefile or in another Makefile included by this one, that declare header files as prerequisites of object files.
– Renaud Pacalet
Nov 23 '18 at 7:03
Yeah,Seems like. But there are lot of make files in this vast project. Is there a way to know from where that rule is hitting ? I mean from which make file its hitting?
– santosh
Nov 23 '18 at 7:07
findandgrep? But beware, some of these included Makefiles may be generated by make itself; before searching them you will have to make sure that they exist already. Moreover, make can also generate dependencies dynamically (using the$(eval...)function); if it is the case searching files will probably not work. You could also use the--debug=vmake option to see what makefiles are parsed.
– Renaud Pacalet
Nov 23 '18 at 7:47
add a comment |
I am new to make. I am trying to debug some issue. For that i kept some debug statements to know all pre-reqs of particular target.
Eg:
$(TARGET_BUILD)/%.o: $(TARGET_BUILD)/%.c
$(info pre-res for this target $^)
$(c_dependency)
After completion of the build. When i check the build log i can see there are several '.h' files listed in prerequisites. From the above target we mentioned only '.c' ($(TARGET_BUILD)/%.c) files as pre-reqs right? Then how come it is showing header files in pre-reqs. Are they auto generated? If yes, Can you please help me how they are created automatically.
FYI, $(c_dependency) is a define directive which has below lines defined :
mkdir -p $(@D)
$(CC64) -o $(@) -c $(CFLAGS64) $<
makefile gnu-make
asked Nov 23 '18 at 6:47
santoshsantosh
495
I am new to make. I am trying to debug some issue. For that i kept some debug statements to know all pre-reqs of particular target.
Eg:
$(TARGET_BUILD)/%.o: $(TARGET_BUILD)/%.c
$(info pre-res for this target $^)
$(c_dependency)
After completion of the build. When i check the build log i can see there are several '.h' files listed in prerequisites. From the above target we mentioned only '.c' ($(TARGET_BUILD)/%.c) files as pre-reqs right? Then how come it is showing header files in pre-reqs. Are they auto generated? If yes, Can you please help me how they are created automatically.
FYI, $(c_dependency) is a define directive which has below lines defined :
mkdir -p $(@D)
$(CC64) -o $(@) -c $(CFLAGS64) $<
makefile gnu-make
makefile gnu-make
asked Nov 23 '18 at 6:47
santoshsantosh
495
asked Nov 23 '18 at 6:47
santoshsantosh
495
edited Nov 23 '18 at 7:35
santosh
asked Nov 23 '18 at 6:47
santoshsantosh
495
asked Nov 23 '18 at 6:47
santoshsantosh
495
asked Nov 23 '18 at 6:47
santoshsantosh
495
495
You probably have other rules without recipe, elsewhere in this Makefile or in another Makefile included by this one, that declare header files as prerequisites of object files.
– Renaud Pacalet
Nov 23 '18 at 7:03
Yeah,Seems like. But there are lot of make files in this vast project. Is there a way to know from where that rule is hitting ? I mean from which make file its hitting?
– santosh
Nov 23 '18 at 7:07
findandgrep? But beware, some of these included Makefiles may be generated by make itself; before searching them you will have to make sure that they exist already. Moreover, make can also generate dependencies dynamically (using the$(eval...)function); if it is the case searching files will probably not work. You could also use the--debug=vmake option to see what makefiles are parsed.
– Renaud Pacalet
Nov 23 '18 at 7:47
add a comment |
You probably have other rules without recipe, elsewhere in this Makefile or in another Makefile included by this one, that declare header files as prerequisites of object files.
– Renaud Pacalet
Nov 23 '18 at 7:03
Yeah,Seems like. But there are lot of make files in this vast project. Is there a way to know from where that rule is hitting ? I mean from which make file its hitting?
– santosh
Nov 23 '18 at 7:07
findandgrep? But beware, some of these included Makefiles may be generated by make itself; before searching them you will have to make sure that they exist already. Moreover, make can also generate dependencies dynamically (using the$(eval...)function); if it is the case searching files will probably not work. You could also use the--debug=vmake option to see what makefiles are parsed.
– Renaud Pacalet
Nov 23 '18 at 7:47
You probably have other rules without recipe, elsewhere in this Makefile or in another Makefile included by this one, that declare header files as prerequisites of object files.
– Renaud Pacalet
Nov 23 '18 at 7:03
You probably have other rules without recipe, elsewhere in this Makefile or in another Makefile included by this one, that declare header files as prerequisites of object files.
– Renaud Pacalet
Nov 23 '18 at 7:03
Yeah,Seems like. But there are lot of make files in this vast project. Is there a way to know from where that rule is hitting ? I mean from which make file its hitting?
– santosh
Nov 23 '18 at 7:07
Yeah,Seems like. But there are lot of make files in this vast project. Is there a way to know from where that rule is hitting ? I mean from which make file its hitting?
– santosh
Nov 23 '18 at 7:07
find and grep? But beware, some of these included Makefiles may be generated by make itself; before searching them you will have to make sure that they exist already. Moreover, make can also generate dependencies dynamically (using the $(eval...) function); if it is the case searching files will probably not work. You could also use the --debug=v make option to see what makefiles are parsed.– Renaud Pacalet
Nov 23 '18 at 7:47
find and grep? But beware, some of these included Makefiles may be generated by make itself; before searching them you will have to make sure that they exist already. Moreover, make can also generate dependencies dynamically (using the $(eval...) function); if it is the case searching files will probably not work. You could also use the --debug=v make option to see what makefiles are parsed.– Renaud Pacalet
Nov 23 '18 at 7:47
add a comment |
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You probably have other rules without recipe, elsewhere in this Makefile or in another Makefile included by this one, that declare header files as prerequisites of object files.
– Renaud Pacalet
Nov 23 '18 at 7:03
Yeah,Seems like. But there are lot of make files in this vast project. Is there a way to know from where that rule is hitting ? I mean from which make file its hitting?
– santosh
Nov 23 '18 at 7:07
findandgrep? But beware, some of these included Makefiles may be generated by make itself; before searching them you will have to make sure that they exist already. Moreover, make can also generate dependencies dynamically (using the$(eval...)function); if it is the case searching files will probably not work. You could also use the--debug=vmake option to see what makefiles are parsed.– Renaud Pacalet
Nov 23 '18 at 7:47