RISCV instructions
I am new to riscv and I am confused between la and lw.
I know that la
stands for load address and lw
stands for load word. If address of VAL is 0x100
and data value of VAL is 0x11
should x3 stores 0x100
and x4 stores 0x11?
la x7, VAL
sw x3, 0(x7)
lw x4, VAL
bne x4, x3
riscv
add a comment |
I am new to riscv and I am confused between la and lw.
I know that la
stands for load address and lw
stands for load word. If address of VAL is 0x100
and data value of VAL is 0x11
should x3 stores 0x100
and x4 stores 0x11?
la x7, VAL
sw x3, 0(x7)
lw x4, VAL
bne x4, x3
riscv
add a comment |
I am new to riscv and I am confused between la and lw.
I know that la
stands for load address and lw
stands for load word. If address of VAL is 0x100
and data value of VAL is 0x11
should x3 stores 0x100
and x4 stores 0x11?
la x7, VAL
sw x3, 0(x7)
lw x4, VAL
bne x4, x3
riscv
I am new to riscv and I am confused between la and lw.
I know that la
stands for load address and lw
stands for load word. If address of VAL is 0x100
and data value of VAL is 0x11
should x3 stores 0x100
and x4 stores 0x11?
la x7, VAL
sw x3, 0(x7)
lw x4, VAL
bne x4, x3
riscv
riscv
edited Nov 21 '18 at 10:37
FabienM
1,116825
1,116825
asked Nov 21 '18 at 5:17
YoungBin JoYoungBin Jo
92
92
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add a comment |
2 Answers
2
active
oldest
votes
la
computes an pointer-sized effective address, but does not perform any memory access. The effective address itself is what is loaded into x7.
(Also note that la
is a pseudo instruction that may expand into two instructions, depending on VAL
— none the less, the sequence computes an effective address and that is its result (no memory access is performed).)
lw
also computes an effective address; however, it uses the effective address in a word-sized memory access, and the result of that memory access is the value loaded into x4.
lb
would do the same as lw
except that the memory access is byte-sized.
As far as your code sequence goes, the value that was in x3
(which cannot be determined from your code snippet) will be stored into memory at locations 0x100-0x103 (this is a word-sized store).
The lw
will reload the value that was written by the sw
. (Note that the lw
in this case may also expand to multiple instructions depending on VAL
, whereas the sw
is a single instruction regardless of VAL
.)
The bne
(though missing a target label) will not branch.
add a comment |
la t0, SYMBOL
is an assembler pesudo instruction that puts the address of SYMBOL
into t0
. Depending on the addressing mode, it expands to something like
lui t0, SYMBOL[31:12]
addi t0, t0, SYMBOL[11:0]
where SYMBOL[31:12]
is the high bits of SYMBOL
, and SYMBOL[11:0]
is the low bits of SYMBOL
-- these aren't valid assembler syntax, and there's some tricks to play with sign extension to get this exactly correct.
lw t0, SYMBOL
is an assembler pseudo instruction that puts the value of memory at the address SYMBOL
into t0
. Depending on the addressing mode, it expands to something like
lui t0, SYMBOL[31:12]
lw t0, SYMBOL[11:0](t0)
Specifically the difference is that lw
performs a load from memory, while la
just generates an address. The sequence
la t0, SYMBOL
lw t0, 0(0)
is functionally equivalent to
lw t0, SYMBOL
but takes an extra instruction, specifically
lui t0, SYMBOL[31:12]
addi t0, t0, SYMBOL[11:0]
lw t0, 0(t0)
vs
lui t0, SYMBOL[31:12]
lw t0, SYMBOL[11:0](t0)
This should all be documentation in the RISC-V Assembly Programmer's Manual, but that is always a work in progress. If you find that's lacking then feel free to submit a patch or open an issue.
add a comment |
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2 Answers
2
active
oldest
votes
2 Answers
2
active
oldest
votes
active
oldest
votes
active
oldest
votes
la
computes an pointer-sized effective address, but does not perform any memory access. The effective address itself is what is loaded into x7.
(Also note that la
is a pseudo instruction that may expand into two instructions, depending on VAL
— none the less, the sequence computes an effective address and that is its result (no memory access is performed).)
lw
also computes an effective address; however, it uses the effective address in a word-sized memory access, and the result of that memory access is the value loaded into x4.
lb
would do the same as lw
except that the memory access is byte-sized.
As far as your code sequence goes, the value that was in x3
(which cannot be determined from your code snippet) will be stored into memory at locations 0x100-0x103 (this is a word-sized store).
The lw
will reload the value that was written by the sw
. (Note that the lw
in this case may also expand to multiple instructions depending on VAL
, whereas the sw
is a single instruction regardless of VAL
.)
The bne
(though missing a target label) will not branch.
add a comment |
la
computes an pointer-sized effective address, but does not perform any memory access. The effective address itself is what is loaded into x7.
(Also note that la
is a pseudo instruction that may expand into two instructions, depending on VAL
— none the less, the sequence computes an effective address and that is its result (no memory access is performed).)
lw
also computes an effective address; however, it uses the effective address in a word-sized memory access, and the result of that memory access is the value loaded into x4.
lb
would do the same as lw
except that the memory access is byte-sized.
As far as your code sequence goes, the value that was in x3
(which cannot be determined from your code snippet) will be stored into memory at locations 0x100-0x103 (this is a word-sized store).
The lw
will reload the value that was written by the sw
. (Note that the lw
in this case may also expand to multiple instructions depending on VAL
, whereas the sw
is a single instruction regardless of VAL
.)
The bne
(though missing a target label) will not branch.
add a comment |
la
computes an pointer-sized effective address, but does not perform any memory access. The effective address itself is what is loaded into x7.
(Also note that la
is a pseudo instruction that may expand into two instructions, depending on VAL
— none the less, the sequence computes an effective address and that is its result (no memory access is performed).)
lw
also computes an effective address; however, it uses the effective address in a word-sized memory access, and the result of that memory access is the value loaded into x4.
lb
would do the same as lw
except that the memory access is byte-sized.
As far as your code sequence goes, the value that was in x3
(which cannot be determined from your code snippet) will be stored into memory at locations 0x100-0x103 (this is a word-sized store).
The lw
will reload the value that was written by the sw
. (Note that the lw
in this case may also expand to multiple instructions depending on VAL
, whereas the sw
is a single instruction regardless of VAL
.)
The bne
(though missing a target label) will not branch.
la
computes an pointer-sized effective address, but does not perform any memory access. The effective address itself is what is loaded into x7.
(Also note that la
is a pseudo instruction that may expand into two instructions, depending on VAL
— none the less, the sequence computes an effective address and that is its result (no memory access is performed).)
lw
also computes an effective address; however, it uses the effective address in a word-sized memory access, and the result of that memory access is the value loaded into x4.
lb
would do the same as lw
except that the memory access is byte-sized.
As far as your code sequence goes, the value that was in x3
(which cannot be determined from your code snippet) will be stored into memory at locations 0x100-0x103 (this is a word-sized store).
The lw
will reload the value that was written by the sw
. (Note that the lw
in this case may also expand to multiple instructions depending on VAL
, whereas the sw
is a single instruction regardless of VAL
.)
The bne
(though missing a target label) will not branch.
answered Nov 22 '18 at 16:26
Erik EidtErik Eidt
2,42011723
2,42011723
add a comment |
add a comment |
la t0, SYMBOL
is an assembler pesudo instruction that puts the address of SYMBOL
into t0
. Depending on the addressing mode, it expands to something like
lui t0, SYMBOL[31:12]
addi t0, t0, SYMBOL[11:0]
where SYMBOL[31:12]
is the high bits of SYMBOL
, and SYMBOL[11:0]
is the low bits of SYMBOL
-- these aren't valid assembler syntax, and there's some tricks to play with sign extension to get this exactly correct.
lw t0, SYMBOL
is an assembler pseudo instruction that puts the value of memory at the address SYMBOL
into t0
. Depending on the addressing mode, it expands to something like
lui t0, SYMBOL[31:12]
lw t0, SYMBOL[11:0](t0)
Specifically the difference is that lw
performs a load from memory, while la
just generates an address. The sequence
la t0, SYMBOL
lw t0, 0(0)
is functionally equivalent to
lw t0, SYMBOL
but takes an extra instruction, specifically
lui t0, SYMBOL[31:12]
addi t0, t0, SYMBOL[11:0]
lw t0, 0(t0)
vs
lui t0, SYMBOL[31:12]
lw t0, SYMBOL[11:0](t0)
This should all be documentation in the RISC-V Assembly Programmer's Manual, but that is always a work in progress. If you find that's lacking then feel free to submit a patch or open an issue.
add a comment |
la t0, SYMBOL
is an assembler pesudo instruction that puts the address of SYMBOL
into t0
. Depending on the addressing mode, it expands to something like
lui t0, SYMBOL[31:12]
addi t0, t0, SYMBOL[11:0]
where SYMBOL[31:12]
is the high bits of SYMBOL
, and SYMBOL[11:0]
is the low bits of SYMBOL
-- these aren't valid assembler syntax, and there's some tricks to play with sign extension to get this exactly correct.
lw t0, SYMBOL
is an assembler pseudo instruction that puts the value of memory at the address SYMBOL
into t0
. Depending on the addressing mode, it expands to something like
lui t0, SYMBOL[31:12]
lw t0, SYMBOL[11:0](t0)
Specifically the difference is that lw
performs a load from memory, while la
just generates an address. The sequence
la t0, SYMBOL
lw t0, 0(0)
is functionally equivalent to
lw t0, SYMBOL
but takes an extra instruction, specifically
lui t0, SYMBOL[31:12]
addi t0, t0, SYMBOL[11:0]
lw t0, 0(t0)
vs
lui t0, SYMBOL[31:12]
lw t0, SYMBOL[11:0](t0)
This should all be documentation in the RISC-V Assembly Programmer's Manual, but that is always a work in progress. If you find that's lacking then feel free to submit a patch or open an issue.
add a comment |
la t0, SYMBOL
is an assembler pesudo instruction that puts the address of SYMBOL
into t0
. Depending on the addressing mode, it expands to something like
lui t0, SYMBOL[31:12]
addi t0, t0, SYMBOL[11:0]
where SYMBOL[31:12]
is the high bits of SYMBOL
, and SYMBOL[11:0]
is the low bits of SYMBOL
-- these aren't valid assembler syntax, and there's some tricks to play with sign extension to get this exactly correct.
lw t0, SYMBOL
is an assembler pseudo instruction that puts the value of memory at the address SYMBOL
into t0
. Depending on the addressing mode, it expands to something like
lui t0, SYMBOL[31:12]
lw t0, SYMBOL[11:0](t0)
Specifically the difference is that lw
performs a load from memory, while la
just generates an address. The sequence
la t0, SYMBOL
lw t0, 0(0)
is functionally equivalent to
lw t0, SYMBOL
but takes an extra instruction, specifically
lui t0, SYMBOL[31:12]
addi t0, t0, SYMBOL[11:0]
lw t0, 0(t0)
vs
lui t0, SYMBOL[31:12]
lw t0, SYMBOL[11:0](t0)
This should all be documentation in the RISC-V Assembly Programmer's Manual, but that is always a work in progress. If you find that's lacking then feel free to submit a patch or open an issue.
la t0, SYMBOL
is an assembler pesudo instruction that puts the address of SYMBOL
into t0
. Depending on the addressing mode, it expands to something like
lui t0, SYMBOL[31:12]
addi t0, t0, SYMBOL[11:0]
where SYMBOL[31:12]
is the high bits of SYMBOL
, and SYMBOL[11:0]
is the low bits of SYMBOL
-- these aren't valid assembler syntax, and there's some tricks to play with sign extension to get this exactly correct.
lw t0, SYMBOL
is an assembler pseudo instruction that puts the value of memory at the address SYMBOL
into t0
. Depending on the addressing mode, it expands to something like
lui t0, SYMBOL[31:12]
lw t0, SYMBOL[11:0](t0)
Specifically the difference is that lw
performs a load from memory, while la
just generates an address. The sequence
la t0, SYMBOL
lw t0, 0(0)
is functionally equivalent to
lw t0, SYMBOL
but takes an extra instruction, specifically
lui t0, SYMBOL[31:12]
addi t0, t0, SYMBOL[11:0]
lw t0, 0(t0)
vs
lui t0, SYMBOL[31:12]
lw t0, SYMBOL[11:0](t0)
This should all be documentation in the RISC-V Assembly Programmer's Manual, but that is always a work in progress. If you find that's lacking then feel free to submit a patch or open an issue.
answered Jan 2 at 18:58
Palmer DabbeltPalmer Dabbelt
4005
4005
add a comment |
add a comment |
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